You're seeing this page as if you were . The main menu is still yours, though. Exit from immersion
Malt Strategy
Arash NejatAN

Arash Nejat

FPGA Prototype & Industrial Hardware Validation

€550/day
Grenoble, FR
8-15 years
FPGA
PCB design
VHDL
Xilinx
hardware

Average response time: 12 hours

About Arash

Spécialiste FPGA orienté prototypage industriel et validation hardware.

J’accompagne les équipes industrielles et les startups deep-tech dans la transformation de designs RTL en prototypes FPGA robustes et prêts pour des environnements techniques exigeants.

Mon expertise couvre :
• Intégration FPGA (Xilinx / Vivado)
• Développement RTL (VHDL / Verilog / SystemVerilog)
• Conception de PCB numériques et capture de schémas
• Design d’alimentation et bring-up carte
• Validation hardware et analyse de signaux

J’interviens de la définition d’architecture et du développement RTL jusqu’au déploiement sur FPGA, l’intégration PCB et la validation complète du système.

Expérience en intégration de systèmes numériques complexes et validation en environnement industriel.

Disponible pour missions industrielles courtes (1–3 mois), développement de prototypes et renfort technique sur projets complexes.

  • English

    Native or bilingual

  • French

    Fluent

Can work on-site
Grenoble (up to 50km)

Experience

  • NovaiCore
    FPGA & Hardware Validation Engineer
    November 2024 - June 2025 (7 months)
    Grenoble, France
    Designed an FPGA-based industrial leveling controller for real-time monitoring and actuation.
    Integrated RS-232 communication, user inputs, relay outputs, and status interfaces.
    Contributed to PCB design and board-level hardware integration.
    Supported hardware validation of sensing, control, and output stages.
    Delivered an embedded control platform combining FPGA logic and custom hardware interfacing.
    FPGA PCB design VHDL Embedded Systems Hardware Validation
  • NovaiCore
    FPGA & Mixed-Signal Engineer
    September 2023 - December 2023 (3 months)
    Grenoble, France
    Implemented a high-speed FPGA interface for ADC/DAC signal-chain bring-up, including converter control, digital data-path integration, timing validation, and real-hardware testing. The project focused on reliable FPGA interfacing with high-speed mixed-signal devices in a performance-oriented hardware platform.
    FPGA Mixed-Signal ADC/DAC Hardware Validation Timing Validation
  • NovaiCore
    FPGA Co-Design Engineer
    March 2023 - August 2023 (5 months)
    Developed an FPGA-based scene matching accelerator using a sliding-window template matching approach with SAD computation. The architecture combined dedicated hardware acceleration for intensive matching operations with on-chip memory management and control logic for efficient image-processing workflows.
    FPGA RTL Image Processing Digital Design Co-Design
Check out Arash's experience

Recommendations

Be the first to recommend Arash

Help this freelancer shine by sharing your experience working together.

These freelancer profiles also match your criteria

AgathaA

Agatha Frydrych

Backend Java Software Engineer

4.7

(3)

2

BaptisteB

Baptiste Duhen

Fullstack developer

4.6

(4)

5

AmedA

Amed Hamou

Senior Lead Developer

4

(2)

7

AudreyA

Audrey Champion

Web developer

4.3

(3)

4

Signup to reveal

Education

  • Doctorat en
    Universite Grenoble Alpes
    2019
    Doctorat en

Skill set

Verilog
RTL
digital design
Vivado
Vérification et validation
Prototyping

Categories